1. Field of the Invention
The present invention relates, in general, to a technique for reducing power consumption of very large scale integrated circuit (VLSI). More particularly, the present invention relates to low power combinational logic circuits utilized in very large scale semiconductor integrated circuits designed in order to effectively reduce power consumption thereof.
2. Description of the Prior Art
The energy necessary for driving CMOS logic circuits is consumed mainly as dynamic power for performing charging and discharging capacitances formed within the circuits. The dynamic power is proportional to the square of the operating voltage supplied to the CMOS logic circuits. The power consumption may be effectively decreased by lowering the operating voltage supplied to the CMOS logic circuits. However, when the operating voltage supplied to the CMOS logic circuits is lowered, the drain current of the transistors of the CMOS logic circuits is diminished and the delay of signal transmission through the CMOS logic circuits is increased, resulting in degradation of the characteristics of the CMOS logic circuits.
For example, if the operating voltage levels supplied to all the constituent gates of a CMOS combinational logic circuit as illustrated in FIG.1 are lowered in the same way for the purpose of saving power, the required timing specification is no longer satisfied with a timing critical path thereof.
On the other hand, usually not all the constituent gates of a CMOS logic circuit are forming timing critical paths. It seems therefore possible to lower only the operating voltage level supplied to the gates which are not forming critical paths and to supply the normal operating voltage level to the gates forming timing critical paths. However, in the case of CMOS logic circuits, level converter circuits must be interposed between each gate given the lowered operating voltage (VDDL) and the subsequent gates given the not lowered normal voltage, called hereinbelow the higher operating voltage (VDDH), for the purpose of preventing DC current from passing through the subsequent gates as described supra.
Next, description is directed to why such level converter circuits have to be provided between each gate given the lowered operating voltage VDDL and the subsequent gates given the higher operating voltage VDDH. Namely, when two different operating voltage levels are utilized to drive transistors designed in the form of CMOS logic circuits, static current may possibly flow through CMOS inverters given the higher operating voltage VDDH as illustrated in FIG. 2.
This is because the p-channel transistor MP1 of the CMOS inverters given the higher operating voltage VDDH can not completely be turned off, if the lowered operating voltage VDDL is lower than the higher operating voltage VDDH minus the threshold voltage Vthp of the p-channel transistor MP1, even when the preceding CMOS inverters given the lowered operating voltage VDDL output a logical high through an n-channel transistor MN1. The DC current passing through the CMOS inverters given the higher operating voltage VDDH is considerably large so that level converter circuits can not be dispensed with between each gate given the lowered operating voltage VDDL and the subsequent gates given the higher operating voltage VDDH.
An example of such a level converter circuit is illustrated in FIG. 3. The level converter circuit comprises a pair of the p-channel transistors MP2 and MP3 with the drain of each transistor connected to the gate of the other. The drain of the p-channel transistor MP2 is connected to ground through an n-channel transistor MN2 which is turned on and off in response to the signal IN from the gate driven with the lowered voltage VDDL. The drain of the other p-channel transistor MP3 is connected to ground through an n-channel transistor MN3 which is turned on and off in response to the signal IN from the gate driven with the lowered voltage VDDL. The n-channel transistors MN2 and MN3 are driven with the lowered voltage VDDL. Since the signal IN is given to the n-channel transistor MN3 through an inverter, one of the transistors MN2 and MN3 is turned on when the other is turned off.
Meanwhile, contrary to the above explained case, any gate given the higher operating voltage VDDH can be directly connected to the subsequent gates given the lowered operating voltage VDDL since no undesirable current passes through the subsequent gates given the lowered operating voltage VDDL whose input nodes receive the VDDH which is higher than the operating voltage of the transistor and therefore the p-channel transistor of the CMOS inverters given the lowered operating voltage VDDL can completely be turned off.
However, while level converter circuits prevent DC current from passing through the subsequent gates as described supra, there is consumed dynamic power during switching thereof when the number of level converter circuits increases. The power saving effect by lowering the operating voltage is therefore reduced by the provision of the level converter circuits.
For example, when some of the constituent gates of a CMOS logic circuit as illustrated in FIG. 1 are given the lowered operating voltage VDDL in accordance with the conventional technique, level converter circuits are interposed as illustrated in FIG. 4. In the figure, the gates given the lower voltage VDDL are distinctively shown by hatching and followed by level converters represented by symbols of checked squares. As seen from the figure, there are provided a number of level converter circuits between gates given the lower voltage VDDL and the gates given the higher operating voltage VDDH.
The provision of a number of level converter circuits substantially increases the total power consumption of the logic circuit and therefore is contradictory to the purpose of saving the operating power of the circuit by lowering the operating voltage supplied to the gates. Accordingly, it has not been tried heretofore to lower the operating voltage supplied to part of the constituent gates of a logic circuit.